FPGA overview	XC3S50	XC3S200	XC3S400
System Gates	50 K	200K	400 K
Logic Cells	1,728	4,320	8,064
Maximum Distributed RAM Bits	12 K	30 K	56 K
Total Block RAM Bits	72 K	216 K	288 K
Maximum user I / O pins (Device)	97	97	97
Maximum user I / O pins ( Board )	90	90	90
Multipliers	Four	12	16
DCMs	2	Four	Four

　■ Equipped with XC3S50-4TQG144C or XC3S200-4TQG144C　
　　　or XC3S400-4TQG144C
　 ■ 90 (91) I / Os are pulled out externally
　 ■ Configuration ROM ( Platform Flash PROM) is standard equipment
　　　. Write / erase more than 20,000 times.
　■ clock
　　　　 48 MHz, 18.432 MHz
　 ■ ISP to the configuration and ROM to the FPGA capable 7 pin JTAG connector equipped
　 ■ with JTAG Buffer circuit, realized downloads stable
　 ■ 3.3V single power supply
　　　1.2V, 2.5V to the board Generated by
　 ■ Reset circuit
　 ■ Credit card size 　　　54mmX86mm ■ 4-layer board RoHS compliant