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Breadboard with Artix-7

FPGA overviewXC7A35TXC7A50TXC7A75TXC7A100TXC7A200T
Logic Cell33,28052,16075,520101,440215,360
Max Distributed RAM (kb)4006008921,1882,888
Max Block RAM (kb)1,8002,7003,7804,86013,140
DSP Slice90120180240740
CMT (MMCMx1 + PLLx1)FiveFive66Ten
GTP Channel (Device)FourFourFourFourFour
GTP Channel ( Board )22222
Max user I / O (Device)250250250285285
Max user I / O ( Board )128128128128128

For details on the FPGA overview, see the XILINX Artix-7 page .

  Equipped with XC7A35T-1FGG484C, XC7A50T-1FGG484C,
    XC7A75T-1FGG484C, XC7A100T-1FGG484C,
    or XC7A200T-1FBG484C
  Abundant I / O extraction (128)
    CNA: 64 (High Range) Vcco = 3.3V
    CNB: 64 (High Range) Vcco = External input
  Onboard clock
    General purpose: 50MHz (LVTTL)
    External input possible (CNA / CNB)
  RocketIO Evaluable
    TX / RX 2ch each
    Reference clock: 125MHz (LVDS), External input possible (MMCX) )
    125 / 150MHz and communication standard
  Configuration ROM
    Quad SPI ROM: N25Q064 / 128 (Micron, 64Mbit / 128Mbit)
    ISP possible from iMPACT
  DDR3 SDRAM installed
    Micron: MT41J64M16 (1Gbit)
 ■ 7-pin JTAG connector installed
    FPGA configuration
    Configuration ROM ISP
    JTAG Buffer circuit Achieves stable download
  3.3V single power supply operation
    1.0V, 1.2V, 1.5V, 1.8V, 2.5V generated in board
    Power sequencer installed (when turned on )
  General-purpose LED x2
  General-purpose switch x2
    Push button switch x1
    DIP switch x1bit
  Reset function for configuration
  Separate Vcco (CNB) (Tested at 3.3V at the time of manufacture)
 8-layer board adopted
  I / O wiring length control (memory is managed separately)

MAX 40.4mm
MIN 20.5mm
MAX 30.9mm
MIN 12.3mm
  • Not all I / O is LVDS compatible

  • Users are requested to consider each I / O standard based on FPGA materials.

  Half card size    54mm x 43mm ■ RoHS directive compliant

Click to enlarge

Click the block diagram

Block Diagram
to enlarge